MI400 GPUs and Helios rack systems extend AMD large-scale AI infrastructure.
AI hardware timeline
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Selection criteria2026
5 entries
A 1,024-card SuperPoD is publicly demonstrated with unified addressing and high-speed links.
Eighth-generation TPUs split into training-oriented 8t and inference-oriented 8i.
950PR launches in the Atlas 350 accelerator card for recommendation and LLM inference.
Rubin GPUs, Vera CPUs, and new interconnects form a new AI compute platform.
2025
8 entries
Third-generation Trainium becomes available through Trn3 UltraServers for training and serving.
GB10 and unified memory move into a desktop system for local model development.
CDNA 4 expands low-precision compute and HBM3e capacity for generative AI.
384 Ascend 910C processors are connected into a unified compute system.
Seventh-generation TPUs target large-scale AI serving with closer chip and system integration.
B300 and GB300 platforms expand memory and inference compute for longer reasoning workloads.
Larger unified-memory configurations increase capacity for running large models locally.
The Blackwell consumer flagship expands to 32 GB of GDDR7 for local AI and graphics workloads.
2024
8 entriesA developer kit combines a software upgrade and lower pricing for edge generative AI.
Trainium2 becomes available through Trn2, expanding custom compute for training and inference.
The MI300 line gains HBM3e for greater generative-AI memory capacity and bandwidth.
Sixth-generation TPUs expand compute, HBM, and interconnect capacity for generative models.
Meta’s custom accelerator serves production ranking and recommendation models in its data centers.
Gaudi 3 combines matrix compute, HBM, and Ethernet links for large-model training and inference.
Blackwell combines a new GPU generation with Grace CPUs and NVLink systems for model training and inference.
The third wafer-scale engine integrates a large compute array and on-chip memory on one wafer.
2023
7 entriesA fifth-generation TPU focused on large-model training is announced with AI Hypercomputer.
Hopper gains HBM3e to increase memory capacity and bandwidth for large-model inference.
Powers the Spark all-in-one system introduced by iFLYTEK and Huawei for enterprise LLM deployment.
Second-generation inference chips power EC2 Inf2 for generative-AI deployment.
2022
5 entriesFirst-generation Trainium becomes generally available through EC2 Trn1 for model training.
Ada and 24 GB of memory support local inference, image generation, and model development.
The second Gaudi generation moves to 7 nm while retaining Ethernet-based training scale-out.
Hopper introduces the Transformer Engine and FP8 for large-model training and inference.
A wafer-on-wafer power-delivery design advances Graphcore’s distributed IPU architecture.
2021
3 entriesCDNA 2 uses a multi-die design to expand memory capacity for training and scientific computing.
The second wafer-scale engine uses a 7 nm process to expand compute and on-chip memory.
2020
5 entriesThe first CDNA architecture targets compute with ROCm support for AI and HPC.
24 GB of memory and Ampere Tensor Cores expand capacity for local model experiments.
Second-generation IPUs use distributed on-chip memory and parallel execution for machine learning.
2019
4 entriesFirst-generation Inferentia becomes available for machine-learning inference through EC2 Inf1.
The first wafer-scale engine integrates compute, memory, and interconnect on one large chip.
2018
4 entries7 nm Vega accelerators introduce PCIe 4.0 for deep learning and HPC.
Huawei announces the Ascend chip family and Da Vinci architecture for inference and training.
2017
2 entriesSecond-generation TPUs add training support and a route to external access through Cloud TPU.
2016
2 entries2014
1 entryAll 54 entries shown